DESIGN

Fundamentals of Semiconductor C-V Measurements

A Universal Test
Capacitance-voltage (C-V) testing is widely used to determine semiconductor parameters, particularly in MOSCAP and MOSFET structures. However, other types of semiconductor devices and technologies can also be characterized with C-V measure­ments, including bipolar junction transistors (BJTs), JFETs, III-V compound devices, photovoltaic cells, MEMs devices, organic TFT displays, photodiodes, carbon nano­tubes (CNTs), and many others.

The fundamental nature of these meas­urements makes them useful in a wide range of applications and disciplines. They are used in the research labs of universities and semiconductor manufacturers to evalu­ate new materials, processes, devices, and circuits. C-V measurements are extremely important to product and yield enhancement engineers, who are responsible for improv­ing processes and device performance. Reliability engineers use these measure­ments to qualify material suppliers, monitor process parameters, and analyze failure mechanisms.

With appropriate methodologies, instru­mentation, and software, a multitude of semiconductor device and material parame­ters can be derived. This information is used all along the production chain beginning with evaluation of epitaxially grown crys­tals, including parameters such as average doping concentration, doping profiles, and carrier lifetimes. In wafer processes, C-V measurements can reveal oxide thickness, oxide charges, mobile ions (contamination), and interface trap density. These measure­ments continue to be used after other process steps, such as lithography, etching, cleaning, dielectric and polysilicon depositions, and metallization. After devices are fully fabri­cated on the wafer, C-V is used to character­ize threshold voltages and other parameters during reliability and basic device testing and to model the performance of these devices.

The Physics of Semiconductor Capacitance
A MOSCAP structure is a fundamental device formed during semiconductor fabri­cation. Although these devices may be used in actual circuits, they are typi­cally integrated into fabrication processes as a test structure. Since they are simple struc­tures and their fabrication is easy to control, they are a convenient way to evaluate the underlying processes.

The metal/polysilicon layer is one plate of the capacitor, and silicon dioxide is the insulator. Since the substrate below the insulating layer is a semiconducting material, it is not by itself the other plate of the capacitor. In effect, the majority charge carriers become the other plate. Physically, capacitance, C, is deter­mined from the variables in the following equation:

C = A (κ/d), where

A is the area of the capacitor,

κ is the dielectric constant of the insulator, and

d is the separation of the two plates.

Therefore, the larger A and κ are, and the thinner the insulator is, the higher the capacitance will be. Typically, semiconduc­tor capacitance values range from nanofar­ads to picofarads, or smaller.

The procedure for taking C-V measure­ments involves the application of DC bias voltages across the capacitor while mak­ing the measurements with an AC signal. Commonly, AC frequencies from about 10kHz to 10MHz are used for these measurements. The bias is applied as a DC voltage sweep that drives the MOSCAP structure from its accumulation region into the depletion region, and then into inversion

A strong DC bias causes majority car­riers in the substrate to accumulate near the insulator interface. Since they can’t get through the insulating layer, capacitance is at a maximum in the accumulation region as the charges stack up near that interface (i.e., d is at a minimum). One of the fundamental parameters that can be derived from C-V accumulation measurements is the silicon dioxide thick­ness, tox.

As bias voltage is decreased, majority carriers get pushed away from the oxide interface and the depletion region forms. When the bias voltage is reversed, charge carriers move the greatest distance from the oxide layer, and capacitance is at a minimum (i.e., d is at a maximum). From this inversion region capacitance, the number of majority carriers can be derived. The same basic concepts apply to MOSFET transistors, even though their physical structure and dop­ing is more complex.

Many other parameters can be derived from the three regions as the bias voltage is swept through them. Different AC signal frequencies can reveal additional details. Low frequen­cies reveal what are called quasistatic characteristics, whereas high frequency testing is more indicative of dynamic performance. Both types of C-V testing are often required.

Basic Test Setup
Because C-V measurements are actually made at AC frequencies, the capacitance for the device under test (DUT) is calculated with the following:

CDUT = IDUT / 2πfVAC, where

IDUT is the magnitude of the AC current through the DUT,

f is the test frequency, and

VAC is the magnitude and phase angle of the measured AC voltage

In other words, the test measures the AC impedance of the DUT by applying an AC voltage and measuring the resulting AC current, AC voltage, and impedance phase angle between them.

These measurements take into account series and parallel resist­ance associated with the capacitance, as well as the dissipation factor (leakage).

Challenges to Successful C-V Measurements
Certain challenges are associated with this testing. Typically, test personnel have problems in the following areas:

Low capacitance measurements (picofarads and smaller values)

C-V instrument connections (through a prober) to the • wafer device

Leaky (high D) capacitance measurements

Using hardware and software to acquire the data

Parameter extractions

Overcoming these challenges requires careful attention to the techniques used along with appropriate hardware and software.

Low Capacitance Measurements. If C is small, the DUT’s AC response current is small and hard to measure. However, at higher frequencies, the DUT impedance is reduced, so the current increases and is easier to measure. Often semiconductor capacitance is very low (less than 1pF), which is below the capabilities of many LCR meters. Even those claiming to measure these small capacitance val­ues may have confusing specifications that make it difficult to deter­mine the final accuracy in the measurement. If accuracy over the instrument’s full measurement range is not explicitly stated, the user needs to clarify this with the manufacturer.

High D (Leaky) Capacitors. In addition to having a low C value, a semiconductor capacitor may also be leaky. That is the case when the equivalent R in parallel with C is too low. This results in resis­tive impedance overwhelming the capacitive impedance, and the C value gets lost in the noise. For devices with ultra-thin oxide layers, D values can be greater than five. In general, as D increases, the accu­racy of a C measurement is rapidly degraded, so high D is a limiting factor in the practical use of a C meter. Again, higher frequencies can help solve the problem. At higher frequencies the capacitive impedance is lower, resulting in a C current that is higher and more easily measured.

C-V Measurement Connections. In most test environments, the DUT is a test structure on a wafer: It is connected to the C-V instru­ment through a prober, a probe card adapter, and a switch matrix. Even if no switch is involved, there is still a prober and significant cabling. At high frequencies, special cor­rections and compensation must be applied. Usually, this is achieved with some combina­tion of an open, short, or calibration device. Because of the complexity of the hardware, cabling, and compensation techniques, it is a good idea to confer with C-V test application engineers. They are skilled at working with various probe systems to overcome many types of interconnection problems.

Obtaining Useful Data. In addition to the accuracy issues mentioned earlier, practical considerations in C-V data collection include the instrumentation’s range of test variables, versatility of parameter extraction software, and ease of hardware usage. Traditionally, C-V testing has been limited to about 30V and 10mA DC bias. However, many appli­cations, such as characterizing LD MOS structures, low-kinterlayer dielectrics, MEMs devices, organic TFT displays, and photodiodes, require tests at higher voltage or current. For these applications, a separate high voltage DC power supply and C meter are required; DC bias up to 400V differen­tial (0 to ±400V) and a current output up to 300mA are very useful. Being able to apply differential DC bias on both the HI and LO terminals of the C-V instrument offers more flexible control over electric fields within the DUT, which is very helpful in the research and modeling of novel devices, such as nano­scale components.

The instrumentation software should include ready-to-run test routines that do not require user programming. These should be available for the most widely used device technologies and test regimens, which were mentioned in the first three paragraphs of this article. Some researchers may also be interested in less common tests, such as performing both a C‑V and C‑f sweep on a Metal‑Insulator‑Metal (MIM) capacitor, measuring small interconnect capacitance on a wafer, or doing a C‑V sweep on a two-terminal nanowire device. The parameter extractions should be easily obtained, with automated curve plotting.

Often, engineers and researchers are expected to perform C-V measurements with little experience and training on the instrumentation. A test system with an intui­tive user interface and easy-to-use features makes this practical. That includes simple test setup, sequence control, and data analy­sis. Otherwise, the user spends more time learning the system than collecting and using the data. Other considerations are a test system with:

• Tightly integrated source-measure units, digital oscilloscope and C-V meter
• Easy integration with other external  instruments
• High resolution and precise measure­ments at the probe tips (DC biasing down to millivolts and capacitance measure­ments down to femtofarads)
• Test setups and libraries that can be eas­ily modified
• Diagnostic/troubleshooting tools that let users know whether or not the system is performing correctly.

About the Author

Lee Stauffer is the Senior Staff Technologist for Keithley Instruments’ Semiconductor Measurements Group, based in Cleveland, Ohio. Prior to joining Keithley, his career included designing satellite communication systems, as well as equipment and product engineering in semiconductor fabs. Keithley designs, develops, manufactures and markets complex electronic instruments and systems geared to the specialized needs of electronics manufacturers for high-performance production testing, process monitoring, product development and research.